1. Field of the Invention
The present invention relates to a multilayered wiring board having incorporated therein a capacitor element, a production process thereof, and a semiconductor device using, such a multilayered wiring board. More particularly, the present invention is directed to the technology for reducing noise generated during simultaneous switching of semiconductor elements mounted on the multilayered wiring board.
2. Description of the Related Art
In recent years, there is a tendency that semiconductor elements are mounted at a high density, and with a high integration degree on a wiring board, to form a semiconductor device. Typical examples of such a semiconductor device which has been practically used include a PGA, i.e., a Pin Grid Array, and a BGA, i.e., a Ball Grid Array. Further, in these semiconductor devices, a multilayered wiring board comprising a plurality of laminated wiring Layers such as a signal layer and a power source layer has been used as the wiring board. In the semiconductor devices, the mounted semiconductor devices are electrically connected with the signal layer and the power source layer.
In addition, the multilayered wiring board has, provided thereon or therein, one or more capacitors. The capacitors act as a storage means for electric charge, and are used for different purposes and thus in different application forms. For example, Japanese Unexamined Patent Publication (Kokai) No. 10-93246 teaches a multilayered wiring board comprising a capacitor sandwiched between the wiring layers of the board to reduce the number of the elements or parts to be packaged in the board to thereby enable high density formation of the wiring along with a reduction in size of the finally produced semiconductor devices. More particularly, the multilayered wiring board of JPP""246, as illustrated in FIG. 1, has a multilayered wiring section 2, and the multilayered wiring section 2 has alternately disposed thin film wiring conductors 4a and 4b and others (not shown) which are electrically connected with each other through a through-hole conductor 9 (partly shown) formed in insulating layers 3a, 3b and 3c made of an organic resin. At least one layer of the organic insulating layers, i.e., layer 3b contains dielectric fillers having a dielectric constant of not less than 20 to form a high dielectric organic insulating layer. Thus, a capacitor is formed between the layer 3b and its lower wiring conductor 4a and upper wiring conductor 4b. Further, the upper wiring conductor 4b is laminated through a nickel layer 10 to an upper surface of the layer 3b to provide good bonding between these layers. Furthermore, the lower wiring conductor 4a has a surface roughness of 0.05 xcexcmxe2x89xa6(Ra)xe2x89xa65 xcexcm to also provide good bonding between this layer and the layer 3b. According to this multilayered wiring board, since a specific capacitor part is not required to be packaged in the board, it becomes possible to reduce the number of the parts to be included in the board.
Referring again to the uses of the capacitors in the multilayered wiring board, they include reducing noise generated during simultaneous switching of the semiconductor element mounted on the wiring board. This noise (hereinafter, referred to as xe2x80x9csimultaneous switching noisexe2x80x9d) is generated as a result of simultaneous on-off operation of the switching elements in the semiconductor element, because such an operation can result in variation of the electrical potential in the source lines and ground lines which are used to supply electric power to the semiconductor element.
To reduce the simultaneous switching noise, it is well-known to insert a capacitor between the source line and the ground line in the multilayered wiring board. That is because, in the presence of the capacitor, the generated noise can be reduced as a result of absorption of the noise by the capacitance of the capacitor. Further, when the capacitor is used in the wiring board for the purpose of reducing the simultaneous switching noise, the noise can be effectively reduced with an increase in the capacity of the capacitor in the board.
Further, if a capacitor""s disposed near the semiconductor element of the multilayered wiring board, a capacitance, in sum, of the capacitor and the wiring connected to the semiconductor element can be increased, because such disposal of the capacitor can reduce the resistance of the wiring connecting between the capacitor and the semiconductor element. Accordingly, it is desired, for the purpose of reducing a simultaneous switching noise, to dispose the capacitor in a neighborhood of the semiconductor element to obtain the shortened wiring distance between the capacitor and the semiconductor element.
Japanese Kokai 10-93246 cited above teaches a multilayered wiring board comprising a capacitor sandwiched between the wiring layers of the board. However, it does not teach use of the sandwiched capacitor in the reduction of the simultaneous switching noise. In addition, it is silent concerning use of a capacitor between the source line and the ground line in the wiring board.
Moreover, the capacitor described in Japanese Kokai 10-93246 has a problem that its capacity cannot be increased to the desired high level, because the capacity is varied depending upon the electrode area of the capacitor, and an upper limit of the electrode area is equivalent to the area of the wiring board having the mounted capacitor. Even if the electrode area of the capacitor is increased to obtain an increased capacity of the capacitor, it is impossible to increase the capacity above the capacity which is determined by the area of the wiring board.
For the above reasons, the capacitor of Japanese Kokai 10-93246 is not considered to be satisfactory as a capacitor for use in reduction of the simultaneous switching noise. It is therefore desired to provide an improved capacitor for use in the multilayered wiring board in which a capacity of the capacitor can be increased to an unexpectedly high Level, thus enabling sufficiently reduce a simultaneous switching noise, if generated
It is therefore an object of the present invention to provide a multilayered wiring board having incorporated therein a capacitor in which the sandwiched capacitor has a large-sized electrode and thus a simultaneous switching noise can be sufficiently reduced.
It is another object of the present invention to provide a process for the production of the improved multilayered wiring board of the present invention.
It is still another object of the present invention to provide a semiconductor device using the improved multilayered wiring board of the present invention.
These and other objects of the present invention will be easily understood from the following detailed description of the preferred embodiments of the present invention.
The inventors of the present invention have conducted intensive studies to accomplish the objects described above, and have discovered an improved multilayered wiring board.
According to one aspect of the present invention, there is provided a multilayered wiring board comprising, at least, two wiring layers and an interlaminar insulating layer sandwiched therebetween, in which said wiring board further has, incorporated therein, at least one capacitor element which comprises a sandwiched structure of:
a lower electrode-forming metallic layer having formed thereon at least one recess portion;
a dielectric layer formed over the lower electrode-forming metallic layer; and
an upper electrode-forming metallic layer formed over the dielectric layer.
According to another aspect of the present invention, there is provided a process for the production of a multilayered wiring board comprising, at least, two is wiring layers and an interlaminar insulating layer sandwiched therebetween, and further having, incorporated therein at least one capacitor element, which process comprises the step of forming said capacitor element by:
forming a metallic layer on a substrate;
forming at least one opening on the metallic layer;
applying a surface covering metallic layer over a full surface of the opening-bearing metallic layer to form a lower electrode-forming metallic layer having formed thereon at least one recess portion;
depositing a dielectric material over the lower electrode-forming metallic layer to form a dielectric layer having a surface profile corresponding to that of the underlying lower electrode-forming metallic layer;
forming an upper electrode-forming metallic layer over the dielectric layer; and
removing the substrate from the resulting capacitor element.
According to still another aspect of the present invention, there is provided a process for the production of a multilayered wiring board comprising, at least, two wiring layers and an interlaminar insulating layer sandwiched therebetween, and further having, incorporated therein, at least one capacitor element, which process comprises the step of forming said capacitor element by:
forming a metallic underlayer on a substrate;
further forming a pattern-forming metallic layer over the metallic underlayer;
fabricating a topographic pattern in the pattern-forming metallic layer to form a lower electrode-forming metallic layer comprising the metallic underlayer having applied theron the patterned metallic layer and having at least one recess on a surface thereof;
depositing a dielectric material over the lower electrode-forming metallic layer to form a dielectric layer having a surface profile corresponding to that of the underlying lower electrode-forming metallic layer;
forming an upper electrode-forming metallic layer over the dielectric layer; and
removing the substrate from the resulting capacitor element.
Further, according to still another aspect of the present invention, there is provided a semiconductor device which comprises a multilayered wiring board comprising, at least, two wiring layers and an interlaminar insulating layer sandwiched therebetween, and further having, incorporated therein, at least one capacitor element which comprises a sandwiched structure of:
a lower electrode-forming metallic layer having formed thereon at least one recess portion;
a dielectric layer formed over the lower electrode-forming metallic layer; and
an upper electrode-forming metallic layer formed over the dielectric layer, and
at least one semiconductor element mounted in or on said multilayered wiring board.